Chronology
Control Your QDR Designs
A step-by-step guide to solving QDR memory data capture challenges with Virtex-II FPGAs.

Get Control of Your High Speed Designs
Chronology and Xilinx team up to solve timing challenges associated with high-speed memory interface designs.

Forte upgrades timing diagram tool
EE Times Online, October 15, 2004

Advancing FPGA design flows using Chronology's TimingDesigner
EDA DesignLine, 4/7/2006

Deterministics
Forecasting Change
QSR Magazine February 2007